The method for manufacturing a semiconductor device generally includes the step of etching an etching layer. For example, reduction of the interval between word lines serving as a gate electrode is important for miniaturizing a flash memory. Japanese PCT Patent Publication No. 2005-522029 discloses the process for forming the word line by etching the polysilicon layer as illustrated in FIGS. 5 to 10. More specifically, an intermediate layer and a top layer (serving as an antireflective film) are formed on the polysilicon, which are etched while using a photoresist as a mask (FIG. 6 in Japanese PCT Patent Publication No. 2005-522029). A side wall layer is formed on the side surfaces of the top and the intermediate layers, and the polysilicon layer is etched to form the word line (FIG. 8 in Japanese PCT Patent Publication No. 2005-522029). The side wall layer allows the interval between the thus formed word lines to be reduced. In the publication, an oxide film and a nitride film are employed as the intermediate layer and the top layer, respectively.
In the aforementioned method, the use of the nitride film as the top layer serving as the antireflective film increases the film thickness of the top layer. As the intermediate layer and the top layer are formed of different materials, the step of eliminating the top layer is required.